同步與非同步複位,以及相關的亞穩態狀況與設計可靠性 | 農藥百科
![同步與非同步複位,以及相關的亞穩態狀況與設計可靠性](https://i.imgur.com/WMTbIbA.jpg)
HowardJohnson在書中(P123頁-3.11.2)用一個flip-flop的例子來說明亞穩態(metastablebehavior)。書中用一個amplifier,兩個switch,一個電容來模擬flip-flop的 ...
![同步與非同步複位,以及相關的亞穩態狀況與設計可靠性](https://i.imgur.com/WMTbIbA.jpg)
非同步複位相比同步複位:
通常情況下(已知複位信號與時鐘的關係),最大的缺點在於非同步複位導致設計變成了非同步時序電路,如果複位信號出現毛刺,將會導致觸發器的誤動作,影響設計的穩定性。 同時,如果複位信號與時鐘關係不確定,將會導致亞穩態情況的出現。下面先給出一個例子,然後就亞穩態進行重點討論。Figure 1 shows an asynchronous race condition where a clock signal is used to reset a flip-flop. When SIG2 is low, the flip-flop is reset to a low state. On the rising edge of SIG2, the designer wants the output to change to the high state of SIG1. Unfortunately, since we don’t know the exact internal timing of the flip-flop or the routing delay of the signal to the clock versus the reset input, we cannot know which signal will arrive first - the clock or the reset. This is a race condition. the clock rising edge appears first, the output will remain low. If the reset signal appears firs...